The present invention relates to a semiconductor device having an internal circuit endowed with latch-up resistance and an I/O-protective circuit endowed with electrostatic surge destruction (ESD) resistance.
Complementary MOS transistor (CMOS) is constituted by combining p-MOS and n-MOS and has been used most widely among various transistors for advantages such as low power consumption, operation even at a low voltage, and the like. In recent years, semiconductor devices having CMOS mounted thereon have come to be used even in severe environments such as space and the like, where the semiconductor devices are exposed to a radiation. When conventional CMOS type semiconductors are used in an environment where a radiation is present, however, there has been a problem in that they malfunction owing to the incidence of charged particles. This malfunction occurs because the charges generated along the track of the charged particles are gathered in the diffused layer according to a mechanism such as funneling or the like, and is called a single-event phenomenon. As the single-event phenomenon, there are, for example, a single-event upset phenomenon in which the gathered charges alter the potential of the node connected to the drain, giving rise to bit reversion; and a single-event latch-up phenomenon which is induced by change of the gathered charges into a trigger current.
Conventional CMOS type semiconductor devices are used by applying a positive voltage to the n-well regions to allow each pn junction between n-well and p-well to be in a reverse bias state. When charged particles pass through the n-well regions of the CMOS transistor, electron-hole pairs appear along the track of the charged particles. At this time, the electrons in the depletion layer are gathered in the n-well regions by drifting and the electrons in the substrate region are gathered also in the n-well regions by diffusion. Further, at the bottom of each n-well region which is in a reverse bias state, the depletion layer is converted into a conducting state by the generated charges, and the electric field which has been applied to the depletion layer, extends towards the p-substrate of low impurity concentration, in a columnar shape. The electrons in this extended electric field region (funneling region) are as well gathered in the n-well regions by drifting. The thus-gathered electrons flow through the n-well regions in a current pulse and become a trigger for latch-up appearance. In this way, single-event latch-up appears.
As an example of the known techniques for suppressing the appearance of latch-up, there is, as disclosed in, for example, JP-A-58-201353, a technique of forming, at the lower part of each well region formed on the principal side of a semiconductor substrate, a high-impurity-concentration region having the same conduction type as the well region. By forming the high-impurity-concentration region, the parasitic transistor formed in each well region is allowed to have a substantially lateral structure, the current amplification ratio is made small, and the appearance of latch-up is suppressed. Further, a technique of forming a high-impurity-concentration region at the lower part of each well region by ion implantation, i.e. a technique of producing a retrograde well, is disclosed in, for example, JP-A-1-130561 and JP-A-4-3920.
In semiconductor devices having, in particular, a twin-well CMOS structure, there is generally employed, as shown in FIG. 4 (prior art), a structure in which both the n-well regions and the p-well regions are retrograde wells. The left side of FIG. 4 is an I/O-protective circuit and the right side is an internal circuit. They are indicated in a separated state but show part of a semiconductor chip. Description is first made on the internal circuit portion. On a p-silicon substrate 101 are formed an n-well region 102 and a p-well region 103. In the internal circuit are also provided an n+-well region 104 of high impurity concentration at the lower part of the n-well region 102, and a p+-well region 105 of high impurity concentration at the lower part of the p-well region 103. On a substrate is formed an element-isolating insulating film 106. On the n-well region 102 is formed a p-channel type MOS transistor consisting of a gate electrode 107 and a p++-region 108; on the p-well region 103 is formed an n-channel type MOS transistor consisting of a gate electrode 109 and an n++-region 110. At the bottom of each gate electrode is present a gate oxide film which is not shown in FIG. 4.
Next, description is made on the I/O-protective circuit. On the semiconductor substrate 101 are formed an n-well region 111 and a p-well region 112. Similarly to the case of the internal circuit, an n+-well region 113 of high impurity concentration is provided at the lower part of the n-well region 111, and a p+-well region 114 of high impurity concentration is provided at the lower part of the p-well region 112. On the substrate is formed an element-isolating insulating film 106. On the n-well region 111 is formed a p-channel type MOS transistor consisting of a gate electrode 115 and a p++-region 116; on the p-well region 112 is formed an n-channel type MOS transistor consisting of a gate electrode 117 and an n++-region 118. At the bottom of each gate electrode is present a gate oxide film which is not shown in FIG. 4.
By employing such a retrograde well structure, the latch-up resistance of CMOS semiconductor device has heretofore been improved.
In conventional semiconductor devices, an I/O-protective circuit has been provided in order to protect the internal circuit from the surge current (voltage) applied to I/O terminals. That is, it has been attempted to protect the internal circuit of conventional semiconductor device from ESD and latch-up caused by the current noise sent from I/O terminals, by allowing the device to have an I/O-protective circuit. However, when a high-impurity-concentration region is formed at the lower part of each well region of I/O-protective circuit, there appears a problem that the latch-up resistance increases but the ESD resistance decreases. This is due to the following reasons.
Firstly, when there is a high-impurity-concentration region at the lower part of each well region of I/O-protective circuit, the current amplification ratio of parasitic bipolar transistor decreases; as a result, the bypassing ability of the ESD current applied from I/O terminals decreases, resulting in reduced ESD resistance.
Secondly, the resistance to shunt the current between the emitter and base of parasitic bipolar transistor, i.e. shunt resistance decreases; as a result, the current injected for operation of lateral bipolar transistor increases and the speed of response becomes low. Therefore, when an electrostatic pulse has been applied, the I/O-protective circuit is unable to make instantaneous response.
Thirdly, the snap-back voltage increases; as a result, the Joule heat generated increases and the thermal breakdown of device occurs easily.
In conventional CMOS semiconductor devices, each n-well region and each n+-well region are formed in one lithography step, and each p-well region and each p+-well region are formed in one lithography step. Therefore, as shown in FIG. 4, a high-impurity-concentration region is present in each well region constituting the internal circuit and I/O-protective circuit of semiconductor chip. As a result, the ESD resistance of the I/O-protective circuit has been insufficient and the I/O-protective circuit has not functioned satisfactorily.
When a semiconductor device having CMOS mounted thereon is used particularly in an environment where a radiation is present, such as space or the like, the internal circuit of the device is required to have single-event latch-up resistance. Consequently, each well region in the internal circuit must comprise a high-impurity-concentration region. Meanwhile, a CMOS semiconductor device must have an I/O-protective circuit regardless of in what kind of environment the device is used, in order to protect the internal circuit from ESD and latch-up caused by the current noise sent from I/O terminals; and this I/O-protective circuit must have ESD resistance. Thus, when a semiconductor device having thereon an internal circuit and an I/O-protective circuit both constituted by CMOS is used in an environment where a radiation is present, such as space or the like, both of good latch-up resistance of internal circuit and good ESD resistance of I/O-protective circuit have been desired strongly.
In order to realize the above desire, the gist of the present invention lies in a semiconductor device having:
an internal circuit having a CMOS comprising a first well region and a second well region both having different conduction types and formed on a semiconductor substrate and each one transistor formed at the first well region and the second well region, and
an I/O-protective circuit having a CMOS comprising a third well region and a fourth well region both having different conduction types and formed on the semiconductor substrate and each one transistor formed at the third well region and the fourth well region, in which semiconductor device
each of the first well region and the second well region comprises a low-impurity-concentration region and a high-impurity-concentration region formed beneath the low-impurity-concentration region, having the same conduction type as the low-impurity-concentration region, and
each of the third well region and the fourth well region comprises a low-impurity-concentration region.
The gist of the present invention lies also in a process for producing a semiconductor device, which comprises:
(a) a step of forming, on a semiconductor substrate, a first photoresist having openings at particular areas,
(b) a step of conducting ion implantation using the first photoresist as a mask, to form a first low-impurity-concentration region as part of an internal circuit to be completed later and a second low-impurity-concentration region as part of an I/O-protective circuit to be completed later,
(c) a step of forming a second photoresist having an opening only above the first low-impurity-concentration region, and
(d) a step of conducting ion implantation using the second photoresist as a mask, to form, at the lower part of the first low-impurity-concentration region, a high-impurity-concentration region having the same conduction type as the first low-impurity-concentration region.
In the semiconductor device of the present invention, a high-impurity-concentration region is formed at the lower part of each well region of the internal circuit, but no high-impurity-concentration region is formed at any well region of the I/O-protective circuit; as a result, both of good latch-up resistance and good ESD resistance are achieved. Further, the semiconductor device of the present invention is endowed with single-event latch-up resistance at the internal circuit and, therefore, can be suitably used in an environment where a radiation is present.
Furthermore, in the process of the present invention for production of semiconductor device, photolithography is conducted twice, which enables selective formation of high-impurity-concentration region at the lower parts of particular well regions. As a result, the semiconductor device of the present invention can be produced inexpensively at a high yield.